This invention relates to a semiconductor lead frame, and more particularly to, a semiconductor lead frame which improves the characteristics and reliability of a semiconductor device using a chip having bonding pads arranged in a cross.
The recent tendency of semiconductors toward high levels of integration with requirements for many inputs and outputs, and high-function makes semiconductor package technology evermore critical. Therefore, it is necessary for a semiconductor lead frame to have greater connection capacity with a high pin count.
In conventional semiconductor package technology, the semiconductor chip is mounted on a lead frame after depositing adhesive materials such as an epoxy on a die pad of the lead frame. In order to miniature the size of the semiconductor package, however, COL(Chip On Lead) or LOC(Lead On Chip) are employed for directly attaching the chip on the lead frame without the die pad, so as to improve the reliability and design of the semiconductor package regardless of the die pad. The LOC has further advantages that it is not necessary to alter the position of a pad of the chip for its predetermined position in response to various kinds of semiconductor packages.
In a conventional structure as illustrated in FIG. 1, the LOC is a straight-shaped lead frame and comprises a rectangular semiconductor chip 10 provided with a plurality of output terminals and associated circuits inner leads 12 having a middle portion of which one side is protruded, and a small and narrow width, the inner leads 12 being arranged with a wide spacing, a plurality of outer leads 16 having outer ends 14 extending at a distance from the inner leads 12 and connected with the inner leads 12, a bus bar 24 formed around the leads 12, at least one insulator 18 disposed between the semiconductor chip 10 and the inner leads 12 for electrically insulating the same, metal wires 20 electrically connecting the inner leads 12 to bonding pads 22 in straight lines arranged at the center portion of the semiconductor chip 10 adjacent to the ends of the inner leads 12, and supporting bar 26 for supporting the inner leads 12. This semiconductor lead frame is suitable for a low pin count package but in a high pin count package, it has a problem in that the size of the chip cannot be increased to increase the number of pins. Accordingly, this results in a further problem that the cost is increased and the properties become degraded.